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C/C++ Source or Header  |  2000-04-23  |  62KB  |  1,836 lines
  1. /***************************************************************************
  2.  
  3.                         -= Kaneko 16 Bit Games =-
  4.  
  5.                 driver by    Luca Elia (eliavit@unina.it)
  6.  
  7.  
  8. CPU   : 68000 ( + MCU )
  9. SOUND : OKI-M6295 x (1 | 2), YM2149 x (0 | 2)
  10.  
  11.  
  12. ---------------------------------------------------------------------------
  13. Game                        Year        Working?    Notes
  14. ---------------------------------------------------------------------------
  15. The Berlin Wall                1991        Yes            Wrong bg colors
  16. Shogun Warriors                1992    ?    No
  17. Great 1000 Miles Rally        1994    *    Yes
  18. Great 1000 Miles Rally 2    1995?    ?    -            The code isn't dumped !
  19. ------------------------------------^--------------------------------------
  20.                                     |
  21.                                     |_ MCU code missing for these games !
  22.  
  23. Note: gtmr manual shows "Compatible with AX Kaneko System Board"
  24.  
  25.  
  26. -----------------------------------------------------------------------------------
  27. Memory Map            RW    gtmr            shogwarr **        berlwall
  28. -----------------------------------------------------------------------------------
  29.  
  30. ROM                    R    000000-0fffff    000000-03ffff    <
  31. Work RAM            RW    100000-10ffff    <                200000-20ffff
  32. MCU: Shared RAM        RW    200000-20ffff    <                -
  33. MCU: Comm.             W    2x0000-2x0001    <                -
  34. Palette                RW    300000-30ffff    380000-380fff    400000-400fff
  35. Sprites             RW    400000-401fff    580000-581fff    30e000-30ffff
  36. Layers 1            RW    500000-503fff    600000-603fff    c00000-c03fff
  37. Layers 2            RW    580000-583fff    *                *
  38. Layers 1 Regs         W    600000-60000f    800000-80000f    d00000-d0001f
  39. Layers 2 Regs         W    680000-68000f    *                *
  40. Screen Regs?         W    700000-70001f    900000-90001f    600000-60003f
  41. M6295 #0            RW    800000-800001    400000-400001    800400-800401
  42. M6295 #1            RW    880000-880001    480000-480001    -
  43. Random Value ?        R    900014-900015    a00014-a00015
  44. Watchdog            RW    a00000-a00001    a80000-a80001    780000-780001(R)
  45. Input Ports            R    b00000-b00007    b80000-b80007    680000-680007
  46. Coin Lockout         W    b80000-b80001    ?                700000-700001
  47. ?                     W    c00000-c00001    ?                480000-480001?
  48. ?                    R    d00000-d00001    < RW            ?
  49. Bankswitching #0     W    e00000-e00001    < Both Chips    -
  50. Bankswitching #1     W    e80000-e80001    -                -
  51. YM2149 #0             RW    -                -                800000-80001f
  52. YM2149 #1             RW    -                -                800200-80021f
  53. Hi-Color Bg Ctrl      W    -                -                500000-500001
  54.                                                         580000-580001
  55.  
  56. -----------------------------------------------------------------------------------
  57. * Unused    ** Preliminary
  58. -----------------------------------------------------------------------------------
  59.  
  60.  
  61. ---------------------------------------------------------------------------
  62.                             Common Issues / To Do
  63. ---------------------------------------------------------------------------
  64.  
  65. - Sprite / Sprite and Sprite / Layers priorities must be made orthogonal
  66.   (This will be possible when the Sprite Manager will support 16 bit gfx)
  67.  
  68. ---------------------------------------------------------------------------
  69.                             Per Game Issues / To Do
  70. ---------------------------------------------------------------------------
  71.  
  72. [berlwall]
  73.  
  74. - Fix colors of the high color background
  75.  
  76.  
  77. [gtmr]
  78.  
  79. - Stage 4: The layers' scrolling is very jerky for a couple of seconds
  80.   in the middle of this level (probably interrupt related)
  81.  
  82. - The layers' colours are not initialised when showing the self test
  83.   screen and the very first screen (with the Kaneko logo in the middle).
  84.   They're probably supposed to be disabled in those occasions, but the
  85.   relevant registers aren't changed throughout the game (?)
  86.  
  87.  Note that there are different revisions of this game.
  88.  
  89.  
  90. [shogwarr]
  91.  
  92. - MCU simulation: the game isn't working
  93.  
  94.  
  95.  
  96. ***************************************************************************/
  97.  
  98. #include "driver.h"
  99. #include "vidhrdw/generic.h"
  100.  
  101. /* Variables only used here: */
  102.  
  103. int shogwarr_mcu_status, shogwarr_mcu_command_offset;
  104. unsigned char *mcu_ram, gtmr_mcu_com[8];
  105.  
  106.  
  107. /* Variables that vidhrdw has access to: */
  108.  
  109.  
  110. /* Variables defined in vidhrdw: */
  111. extern unsigned char *kaneko16_bgram, *kaneko16_fgram;
  112. extern unsigned char *kaneko16_layers1_regs, *kaneko16_layers2_regs, *kaneko16_screen_regs;
  113. extern unsigned char *kaneko16_bg15_select, *kaneko16_bg15_reg;
  114. extern int kaneko16_spritetype;
  115.  
  116. /* Functions defined in vidhrdw: */
  117.  
  118. WRITE_HANDLER( kaneko16_paletteram_w );
  119. WRITE_HANDLER( gtmr_paletteram_w );
  120.  
  121. WRITE_HANDLER( kaneko16_layers1_w );
  122.  
  123. WRITE_HANDLER( kaneko16_layers1_regs_w );
  124. WRITE_HANDLER( kaneko16_layers2_regs_w );
  125.  
  126. READ_HANDLER( kaneko16_screen_regs_r );
  127. WRITE_HANDLER( kaneko16_screen_regs_w );
  128.  
  129. READ_HANDLER( kaneko16_bg15_select_r );
  130. WRITE_HANDLER( kaneko16_bg15_select_w );
  131.  
  132. READ_HANDLER( kaneko16_bg15_reg_r );
  133. WRITE_HANDLER( kaneko16_bg15_reg_w );
  134.  
  135. int  kaneko16_vh_start(void);
  136. void kaneko16_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
  137.  
  138. void berlwall_init_palette(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
  139. int  berlwall_vh_start(void);
  140. void berlwall_vh_stop(void);
  141.  
  142.  
  143.  
  144.  
  145. static void gtmr_init_machine (void)
  146. {
  147.     kaneko16_bgram = kaneko16_fgram + 0x1000;
  148.     kaneko16_spritetype = 1;    // "standard" sprites
  149.  
  150.     memset(gtmr_mcu_com,0,8);
  151. }
  152.  
  153.  
  154. static void shogwarr_init_machine (void)
  155. {
  156.     kaneko16_bgram = kaneko16_fgram + 0x1000;
  157.     kaneko16_spritetype = 0;    // differently mapped attribute word
  158.  
  159.     shogwarr_mcu_status = 0;
  160.     shogwarr_mcu_command_offset = 0;
  161. }
  162.  
  163.  
  164. static void berlwall_init_machine (void)
  165. {
  166.     kaneko16_bgram = kaneko16_fgram + 0x1000;
  167.     kaneko16_spritetype = 2;    // like type 0, but using 16 instead of 8 bytes
  168. }
  169.  
  170.  
  171.  
  172.  
  173. /***************************************************************************
  174.  
  175.                             MCU Code simulation
  176.  
  177. ***************************************************************************/
  178.  
  179.  
  180.  
  181. /***************************************************************************
  182.                         [ Great 1000 Miles Rally ]
  183. ***************************************************************************/
  184.  
  185. struct GameDriver driver_gtmr;
  186. struct GameDriver driver_gtmre;
  187.  
  188. /* The MCU has access to NVRAM */
  189. void gtmr_mcu_run(void)
  190. {
  191.     int mcu_command    =    READ_WORD(&mcu_ram[0x0010]);
  192.     int mcu_offset    =    READ_WORD(&mcu_ram[0x0012]);
  193.     int mcu_data    =    READ_WORD(&mcu_ram[0x0014]);
  194.  
  195.     logerror("CPU #0 PC %06X : MCU executed command: %04X %04X %04X\n",cpu_get_pc(),mcu_command,mcu_offset,mcu_data);
  196.  
  197.     switch (mcu_command >> 8)
  198.     {
  199.  
  200.         case 0x02:    // Read from NVRAM
  201.         {
  202.             void *f;
  203.             if ((f = osd_fopen(Machine->gamedrv->name,0,OSD_FILETYPE_NVRAM,0)) != 0)
  204.             {
  205.                 osd_fread(f,&mcu_ram[mcu_offset], 128);
  206.                 osd_fclose(f);
  207.             }
  208.         }
  209.         break;
  210.  
  211.         case 0x42:    // Write to NVRAM
  212.         {
  213.             void *f;
  214.             if ((f = osd_fopen(Machine->gamedrv->name,0,OSD_FILETYPE_NVRAM,1)) != 0)
  215.             {
  216.                 osd_fwrite(f,&mcu_ram[mcu_offset], 128);
  217.                 osd_fclose(f);
  218.             }
  219.         }
  220.         break;
  221.  
  222.         case 0x03:    // DSW
  223.         {
  224.             WRITE_WORD(&mcu_ram[mcu_offset], readinputport(4));
  225.         }
  226.         break;
  227.  
  228.         case 0x04:    // TEST (2 versions)
  229.         {
  230.             if (Machine->gamedrv == &driver_gtmr)
  231.             {
  232.                 /* MCU writes the string "MM0525-TOYBOX199" to shared ram */
  233.                 WRITE_WORD(&mcu_ram[mcu_offset+0x00], 0x4d4d );
  234.                 WRITE_WORD(&mcu_ram[mcu_offset+0x02], 0x3035 );
  235.                 WRITE_WORD(&mcu_ram[mcu_offset+0x04], 0x3235 );
  236.                 WRITE_WORD(&mcu_ram[mcu_offset+0x06], 0x2d54 );
  237.                 WRITE_WORD(&mcu_ram[mcu_offset+0x08], 0x4f59 );
  238.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0a], 0x424f );
  239.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0c], 0x5831 );
  240.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0e], 0x3939 );
  241.             }
  242.  
  243.             if (Machine->gamedrv == &driver_gtmre)
  244.             {
  245.                 /* MCU writes the string "USMM0713-TB1994 " to shared ram */
  246.                 WRITE_WORD(&mcu_ram[mcu_offset+0x00], 0x5553 );
  247.                 WRITE_WORD(&mcu_ram[mcu_offset+0x02], 0x4d4d );
  248.                 WRITE_WORD(&mcu_ram[mcu_offset+0x04], 0x3037 );
  249.                 WRITE_WORD(&mcu_ram[mcu_offset+0x06], 0x3133 );
  250.                 WRITE_WORD(&mcu_ram[mcu_offset+0x08], 0x2d54 );
  251.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0a], 0x4231 );
  252.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0c], 0x3939 );
  253.                 WRITE_WORD(&mcu_ram[mcu_offset+0x0e], 0x3420 );
  254.             }
  255.         }
  256.         break;
  257.     }
  258.  
  259. }
  260.  
  261.  
  262. #define GTMR_MCU_COM_W(_n_) \
  263. WRITE_HANDLER( gtmr_mcu_com##_n_##_w ) \
  264. { \
  265.     COMBINE_WORD_MEM(>mr_mcu_com[_n_ * 2], data); \
  266.     if (READ_WORD(>mr_mcu_com[0]) != 0xFFFF)    return; \
  267.     if (READ_WORD(>mr_mcu_com[2]) != 0xFFFF)    return; \
  268.     if (READ_WORD(>mr_mcu_com[4]) != 0xFFFF)    return; \
  269.     if (READ_WORD(>mr_mcu_com[6]) != 0xFFFF)    return; \
  270. \
  271.     memset(gtmr_mcu_com,0,8); \
  272.     gtmr_mcu_run(); \
  273. }
  274.  
  275. GTMR_MCU_COM_W(0)
  276. GTMR_MCU_COM_W(1)
  277. GTMR_MCU_COM_W(2)
  278. GTMR_MCU_COM_W(3)
  279.  
  280.  
  281.  
  282.  
  283. /***************************************************************************
  284.                             [ Shogun Warriors ]
  285. ***************************************************************************/
  286.  
  287. /* Preliminary simulation: the game doesn't work */
  288.  
  289. /* The MCU has access to NVRAM */
  290. void shogwarr_mcu_run(void)
  291. {
  292.     int mcu_command;
  293.  
  294.     if ( shogwarr_mcu_status != (1|2|4|8) )    return;
  295.  
  296.     mcu_command = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset]);
  297.  
  298.     if (!mcu_command) return;
  299.  
  300.     logerror("CPU #0 PC %06X : MCU executed command at %04X: %04X\n",
  301.          cpu_get_pc(),shogwarr_mcu_command_offset,mcu_command);
  302.  
  303.     switch (mcu_command)
  304.     {
  305.  
  306.         case 0x00ff:
  307.         {
  308.             int param1 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0002]);
  309.             int param2 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0004]);
  310.             int param3 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0006]);
  311. //            int param4 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0008]);
  312.             int param5 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000a]);
  313. //            int param6 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000c]);
  314. //            int param7 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000e]);
  315.  
  316.             // clear old command (handshake to main cpu)
  317.             WRITE_WORD(&mcu_ram[shogwarr_mcu_command_offset], 0x0000);
  318.  
  319.             // execute the command:
  320.  
  321.             COMBINE_WORD_MEM(&mcu_ram[param1 & (~1)],
  322.                 (param1 & 1) ?
  323.                     (0xff000000 | (~readinputport(4)<<0) ) :
  324.                     (0x00ff0000 | (~readinputport(4)<<8) ) );    // DSW
  325.  
  326.             COMBINE_WORD_MEM(&mcu_ram[param2 & (~1)],
  327.                 (param2 & 1) ?
  328.                     (0xff000000 | (0xff<<0) ) :
  329.                     (0x00ff0000 | (0xff<<8) ) );    // ? -1 / anything else
  330.  
  331.             shogwarr_mcu_command_offset = param3;    // where next command will be written?
  332.             // param 4?
  333.             WRITE_WORD(&mcu_ram[param5], 0x8ee4);    // MCU Rom Checksum
  334.             // param 6&7 = address.l
  335.         }
  336.         break;
  337.  
  338.  
  339.         case 0x0001:
  340.         {
  341. //            int param1 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0002]);
  342.             int param2 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0004]);
  343.  
  344.             // clear old command (handshake to main cpu)
  345.             WRITE_WORD(&mcu_ram[shogwarr_mcu_command_offset], 0x0000);
  346.  
  347.             // execute the command:
  348.  
  349.             // param1 ?
  350.             WRITE_WORD(&mcu_ram[param2+0x0000], 0x0000 );    // ?
  351.             WRITE_WORD(&mcu_ram[param2+0x0002], 0x0000 );    // ?
  352.             WRITE_WORD(&mcu_ram[param2+0x0004], 0x0000 );    // ?
  353.  
  354.             WRITE_WORD(&mcu_ram[param2+0x0006], 0x0000 );    // ? addr.l
  355.             WRITE_WORD(&mcu_ram[param2+0x0008], 0x00e0 );    // 0000e0: 4e73 rte
  356.  
  357.         }
  358.         break;
  359.  
  360.  
  361.         case 0x0002:
  362.         {
  363. //            int param1 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0002]);
  364. //            int param2 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0004]);
  365. //            int param3 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0006]);
  366. //            int param4 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x0008]);
  367. //            int param5 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000a]);
  368. //            int param6 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000c]);
  369. //            int param7 = READ_WORD(&mcu_ram[shogwarr_mcu_command_offset + 0x000e]);
  370.  
  371.             // clear old command (handshake to main cpu)
  372.             WRITE_WORD(&mcu_ram[shogwarr_mcu_command_offset], 0x0000);
  373.  
  374.             // execute the command:
  375.  
  376.         }
  377.         break;
  378.  
  379.     }
  380.  
  381. }
  382.  
  383.  
  384.  
  385. WRITE_HANDLER( shogwarr_mcu_ram_w )
  386. {
  387.     COMBINE_WORD_MEM(&mcu_ram[offset], data);
  388.     shogwarr_mcu_run();
  389. }
  390.  
  391.  
  392.  
  393. #define SHOGWARR_MCU_COM_W(_n_) \
  394. WRITE_HANDLER( shogwarr_mcu_com##_n_##_w ) \
  395. { \
  396.     shogwarr_mcu_status |= (1 << _n_); \
  397.     shogwarr_mcu_run(); \
  398. }
  399.  
  400. SHOGWARR_MCU_COM_W(0)
  401. SHOGWARR_MCU_COM_W(1)
  402. SHOGWARR_MCU_COM_W(2)
  403. SHOGWARR_MCU_COM_W(3)
  404.  
  405.  
  406.  
  407.  
  408.  
  409. /***************************************************************************
  410.  
  411.                                 Memory Maps
  412.  
  413. ***************************************************************************/
  414.  
  415.  
  416. READ_HANDLER( kaneko16_rnd_r )
  417. {
  418.     return rand();
  419. }
  420.  
  421. /* bit 0 of this byte is set after a coin insertion,
  422.    then reset after a short while */
  423. WRITE_HANDLER( kaneko16_coin_lockout_w )
  424. {
  425.     if (!(data & 0xff000000))
  426.     {
  427.         coin_lockout_w(0, ((~data) >> 11) & 1 );
  428.         coin_lockout_w(1, ((~data) >> 10) & 1 );
  429.     }
  430. }
  431.  
  432.  
  433. /***************************************************************************
  434.                             [ The Berlin Wall ]
  435. ***************************************************************************/
  436.  
  437. #define BERLWALL_YM2149_RW(_n_) \
  438. \
  439. READ_HANDLER( berlwall_YM2149_##_n_##_r ) \
  440. { \
  441.     /* Each 2149 register is mapped to a different address */ \
  442.     AY8910_control_port_##_n_##_w(0,offset/2); \
  443.     return AY8910_read_port_##_n_##_r(0); \
  444. } \
  445. \
  446. WRITE_HANDLER( berlwall_YM2149_##_n_##_w ) \
  447. { \
  448.     /* Each 2149 register is mapped to a different address */ \
  449.     AY8910_control_port_##_n_##_w(0,offset / 2); \
  450.     /* The registers are mapped to odd addresses, except one! */ \
  451.     if ((data & 0x00ff0000)==0)    AY8910_write_port_##_n_##_w(0, data       & 0xff); \
  452.     else                        AY8910_write_port_##_n_##_w(0,(data >> 8) & 0xff); \
  453. }
  454.  
  455. /* Two identically mapped chips */
  456. BERLWALL_YM2149_RW(0)
  457. BERLWALL_YM2149_RW(1)
  458.  
  459.  
  460. static struct MemoryReadAddress berlwall_readmem[] =
  461. {
  462.     { 0x000000, 0x03ffff, MRA_ROM                    },    // ROM
  463.     { 0x200000, 0x20ffff, MRA_BANK1                    },    // RAM
  464.     { 0x30e000, 0x30ffff, MRA_BANK2                    },    // Sprites
  465.     { 0x400000, 0x400fff, MRA_BANK3                    },    // Palette
  466. //    { 0x480000, 0x480001, MRA_BANK4                    },    // ?
  467.     { 0x500000, 0x500001, kaneko16_bg15_reg_r        },    // High Color Background
  468.     { 0x580000, 0x580001, kaneko16_bg15_select_r    },
  469.     { 0x600000, 0x60003f, MRA_BANK5                    },    // Screen Regs ?
  470.     { 0x680000, 0x680001, input_port_0_r            },    // Inputs
  471.     { 0x680002, 0x680003, input_port_1_r            },
  472.     { 0x680004, 0x680005, input_port_2_r            },
  473. //    { 0x680006, 0x680007, input_port_3_r            },
  474.     { 0x780000, 0x780001, watchdog_reset_r            },    // Watchdog
  475.     { 0x800000, 0x80001f, berlwall_YM2149_0_r        },    // Sound
  476.     { 0x800200, 0x80021f, berlwall_YM2149_1_r        },
  477.     { 0x800400, 0x800401, OKIM6295_status_0_r        },
  478.     { 0xc00000, 0xc03fff, MRA_BANK7                    },    // Layers 1
  479.     { 0xd00000, 0xd0001f, MRA_BANK8                    },    // Layers 1 Regs
  480.     { -1 }
  481. };
  482.  
  483. static struct MemoryWriteAddress berlwall_writemem[] =
  484. {
  485.     { 0x000000, 0x03ffff, MWA_ROM                                            },    // ROM
  486.     { 0x200000, 0x20ffff, MWA_BANK1                                            },    // RAM
  487.     { 0x30e000, 0x30ffff, MWA_BANK2, &spriteram, &spriteram_size            },    // Sprites
  488.     { 0x400000, 0x400fff, kaneko16_paletteram_w, &paletteram                },    // Palette
  489. //    { 0x480000, 0x480001, MWA_BANK4                                            },    // ?
  490.     { 0x500000, 0x500001, kaneko16_bg15_reg_w, &kaneko16_bg15_reg            },    // High Color Background
  491.     { 0x580000, 0x580001, kaneko16_bg15_select_w, &kaneko16_bg15_select        },
  492.     { 0x600000, 0x60003f, kaneko16_screen_regs_w, &kaneko16_screen_regs        },    // Screen Regs ?
  493.     { 0x700000, 0x700001, kaneko16_coin_lockout_w                            },    // Coin Lockout
  494.     { 0x800000, 0x80001f, berlwall_YM2149_0_w                                },    // Sound
  495.     { 0x800200, 0x80021f, berlwall_YM2149_1_w                                },
  496.     { 0x800400, 0x800401, OKIM6295_data_0_w                                    },
  497.     { 0xc00000, 0xc03fff, kaneko16_layers1_w, &kaneko16_fgram                },    // Layers 1
  498.     { 0xd00000, 0xd0001f, kaneko16_layers1_regs_w, &kaneko16_layers1_regs    },    // Layers 1 Regs
  499.     { -1 }
  500. };
  501.  
  502.  
  503.  
  504.  
  505. /***************************************************************************
  506.                         [ Great 1000 Miles Rally ]
  507. ***************************************************************************/
  508.  
  509.  
  510. READ_HANDLER( gtmr_wheel_r )
  511. {
  512.     if ( (readinputport(4) & 0x1800) == 0x10)    // DSW setting
  513.         return    readinputport(5)<<8;            // 360° Wheel
  514.     else
  515.         return    readinputport(5);                // 270° Wheel
  516. }
  517.  
  518. static int bank0;
  519. WRITE_HANDLER( gtmr_oki_0_bank_w )
  520. {
  521.     OKIM6295_set_bank_base(0, ALL_VOICES, 0x10000 * (data & 0xF) );
  522.     bank0 = (data & 0xF);
  523. //    logerror("CPU #0 PC %06X : OKI0 bank %08X\n",cpu_get_pc(),data);
  524. }
  525.  
  526. WRITE_HANDLER( gtmr_oki_1_bank_w )
  527. {
  528.     OKIM6295_set_bank_base(1, ALL_VOICES, 0x40000 * (data & 0x1) );
  529. //    logerror("CPU #0 PC %06X : OKI1 bank %08X\n",cpu_get_pc(),data);
  530. }
  531.  
  532. /*
  533.     If you look at the samples ROM for the OKI chip #0, you'll see
  534.     it's divided into 16 chunks, each chunk starting with the header
  535.     holding the samples    addresses. But, except for chunk 0, the first
  536.     $100 bytes ($20 samples) of each chunk are empty, and despite that,
  537.     samples in the range $0-1f are played. So, whenever a samples in
  538.     this range is requested, we use the address and sample from chunk 0,
  539.     otherwise we use those from the selected bank. By using this scheme
  540.     the sound improves, but I wouldn't bet it's correct..
  541. */
  542.  
  543. WRITE_HANDLER( gtmr_oki_0_data_w )
  544. {
  545.     static int pend = 0;
  546.  
  547.     if (pend)    pend = 0;
  548.     else
  549.     {
  550.         if (data & 0x80)
  551.         {
  552.             int samp = data &0x7f;
  553.  
  554.             pend = 1;
  555.             if (samp < 0x20)
  556.             {
  557.                 OKIM6295_set_bank_base(0, ALL_VOICES, 0);
  558. //                logerror("Setting OKI0 bank to zero\n");
  559.             }
  560.             else
  561.                 OKIM6295_set_bank_base(0, ALL_VOICES, 0x10000 * bank0 );
  562.         }
  563.     }
  564.  
  565.     OKIM6295_data_0_w(offset,data);
  566. //    logerror("CPU #0 PC %06X : OKI0 <- %08X\n",cpu_get_pc(),data);
  567. }
  568.  
  569. WRITE_HANDLER( gtmr_oki_1_data_w )
  570. {
  571.     OKIM6295_data_1_w(offset,data);
  572. //    logerror("CPU #0 PC %06X : OKI1 <- %08X\n",cpu_get_pc(),data);
  573. }
  574.  
  575.  
  576.  
  577.  
  578. static struct MemoryReadAddress gtmr_readmem[] =
  579. {
  580.     { 0x000000, 0x0ffffd, MRA_ROM                    },    // ROM
  581.     { 0x0ffffe, 0x0fffff, gtmr_wheel_r                },    // Wheel Value
  582.     { 0x100000, 0x10ffff, MRA_BANK1                    },    // RAM
  583.     { 0x200000, 0x20ffff, MRA_BANK2                    },    // Shared With MCU
  584.     { 0x300000, 0x327fff, MRA_BANK3                    },    // Palette (300000-30ffff)
  585.     { 0x400000, 0x401fff, MRA_BANK4                    },    // Sprites
  586.     { 0x500000, 0x503fff, MRA_BANK5                    },    // Layers 1
  587.     { 0x580000, 0x583fff, MRA_BANK6                    },    // Layers 2
  588.     { 0x600000, 0x60000f, MRA_BANK7                    },    // Layers 1 Regs
  589.     { 0x680000, 0x68000f, MRA_BANK8                    },    // Layers 2 Regs
  590.     { 0x700000, 0x70001f, kaneko16_screen_regs_r    },    // Screen Regs ?
  591.     { 0x800000, 0x800001, OKIM6295_status_0_r        },    // Samples
  592.     { 0x880000, 0x880001, OKIM6295_status_1_r        },
  593.     { 0x900014, 0x900015, kaneko16_rnd_r            },    // Random Number ?
  594.     { 0xa00000, 0xa00001, watchdog_reset_r            },    // Watchdog
  595.     { 0xb00000, 0xb00001, input_port_0_r            },    // Inputs
  596.     { 0xb00002, 0xb00003, input_port_1_r            },
  597.     { 0xb00004, 0xb00005, input_port_2_r            },
  598.     { 0xb00006, 0xb00007, input_port_3_r            },
  599.     { 0xd00000, 0xd00001, MRA_NOP                    },    // ? (bit 0)
  600.     { -1 }
  601. };
  602.  
  603. static struct MemoryWriteAddress gtmr_writemem[] =
  604. {
  605.     { 0x000000, 0x0fffff, MWA_ROM                    },    // ROM
  606.     { 0x100000, 0x10ffff, MWA_BANK1                    },    // RAM
  607.     { 0x200000, 0x20ffff, MWA_BANK2, &mcu_ram        },    // Shared With MCU
  608.     { 0x2a0000, 0x2a0001, gtmr_mcu_com0_w            },    // To MCU ?
  609.     { 0x2b0000, 0x2b0001, gtmr_mcu_com1_w            },
  610.     { 0x2c0000, 0x2c0001, gtmr_mcu_com2_w            },
  611.     { 0x2d0000, 0x2d0001, gtmr_mcu_com3_w            },
  612.     { 0x300000, 0x327fff, gtmr_paletteram_w, &paletteram                    },    // Palette
  613.     { 0x400000, 0x401fff, MWA_BANK4, &spriteram, &spriteram_size            },    // Sprites
  614.     { 0x500000, 0x503fff, kaneko16_layers1_w, &kaneko16_fgram                },    // Layers 1
  615.     { 0x580000, 0x583fff, MWA_BANK6                                            },    // Layers 2
  616.     { 0x600000, 0x60000f, kaneko16_layers1_regs_w, &kaneko16_layers1_regs    },    // Layers 1 Regs
  617.     { 0x680000, 0x68000f, kaneko16_layers2_regs_w, &kaneko16_layers2_regs    },    // Layers 2 Regs
  618.     { 0x700000, 0x70001f, kaneko16_screen_regs_w, &kaneko16_screen_regs        },    // Screen Regs ?
  619.     { 0x800000, 0x800001, gtmr_oki_0_data_w            },    // Samples
  620.     { 0x880000, 0x880001, gtmr_oki_1_data_w            },
  621.     { 0xa00000, 0xa00001, watchdog_reset_w            },    // Watchdog
  622.     { 0xb80000, 0xb80001, kaneko16_coin_lockout_w    },    // Coin Lockout
  623. //    { 0xc00000, 0xc00001, MWA_NOP                    },    // ?
  624.     { 0xe00000, 0xe00001, gtmr_oki_0_bank_w            },    // Samples Bankswitching
  625.     { 0xe80000, 0xe80001, gtmr_oki_1_bank_w            },
  626.     { -1 }
  627. };
  628.  
  629.  
  630.  
  631.  
  632. /***************************************************************************
  633.                             [ Shogun Warriors ]
  634. ***************************************************************************/
  635.  
  636. /* Untested */
  637. WRITE_HANDLER( shogwarr_oki_bank_w )
  638. {
  639.     OKIM6295_set_bank_base(0, ALL_VOICES, 0x10000 * ((data >> 0) & 0x3) );
  640.     OKIM6295_set_bank_base(1, ALL_VOICES, 0x10000 * ((data >> 4) & 0x3) );
  641. }
  642.  
  643. static struct MemoryReadAddress shogwarr_readmem[] =
  644. {
  645.     { 0x000000, 0x03ffff, MRA_ROM                },    // ROM
  646.     { 0x100000, 0x10ffff, MRA_BANK1                },    // RAM
  647.     { 0x200000, 0x20ffff, MRA_BANK2                },    // Shared With MCU
  648.     { 0x380000, 0x380fff, MRA_BANK3                },    // Palette
  649.     { 0x400000, 0x400001, OKIM6295_status_0_r    },    // Samples
  650.     { 0x480000, 0x480001, OKIM6295_status_1_r    },
  651.     { 0x580000, 0x581fff, MRA_BANK4                },    // Sprites
  652.     { 0x600000, 0x603fff, MRA_BANK6                },    // Layers 1
  653.     { 0x800000, 0x80000f, MRA_BANK7                },    // Layers 1 Regs
  654.     { 0x900000, 0x90001f, MRA_BANK8                },    // Screen Regs ?
  655.     { 0xa00014, 0xa00015, kaneko16_rnd_r        },    // Random Number ?
  656.     { 0xa80000, 0xa80001, watchdog_reset_r        },    // Watchdog
  657.     { 0xb80000, 0xb80001, input_port_0_r        },    // Inputs
  658.     { 0xb80002, 0xb80003, input_port_1_r        },
  659.     { 0xb80004, 0xb80005, input_port_2_r        },
  660.     { 0xb80006, 0xb80007, input_port_3_r        },
  661.     { 0xd00000, 0xd00001, MRA_NOP                },    // ? (bit 0)
  662.     { -1 }
  663. };
  664. static struct MemoryWriteAddress shogwarr_writemem[] =
  665. {
  666.     { 0x000000, 0x03ffff, MWA_ROM                                },    // ROM
  667.     { 0x100000, 0x10ffff, MWA_BANK1                                },    // RAM
  668.     { 0x200000, 0x20ffff, shogwarr_mcu_ram_w, &mcu_ram            },    // Shared With MCU
  669.     { 0x280000, 0x280001, shogwarr_mcu_com0_w                    },    // To MCU ?
  670.     { 0x290000, 0x290001, shogwarr_mcu_com1_w                    },
  671.     { 0x2b0000, 0x2b0001, shogwarr_mcu_com2_w                    },
  672.     { 0x2d0000, 0x2d0001, shogwarr_mcu_com3_w                    },
  673.     { 0x380000, 0x380fff, kaneko16_paletteram_w, &paletteram    },    // Palette
  674.     { 0x400000, 0x400001, OKIM6295_data_0_w                        },    // Samples
  675.     { 0x480000, 0x480001, OKIM6295_data_1_w                        },
  676.     { 0x580000, 0x581fff, MWA_BANK4, &spriteram, &spriteram_size            },    // Sprites
  677.     { 0x600000, 0x603fff, kaneko16_layers1_w, &kaneko16_fgram                },    // Layers 1
  678.     { 0x800000, 0x80000f, kaneko16_layers1_regs_w, &kaneko16_layers1_regs    },    // Layers 1 Regs
  679.     { 0x900000, 0x90001f, kaneko16_screen_regs_w, &kaneko16_screen_regs        },    // Screen Regs ?
  680.     { 0xa80000, 0xa80001, watchdog_reset_w                        },    // Watchdog
  681.     { 0xd00000, 0xd00001, MWA_NOP                                },    // ?
  682.     { 0xe00000, 0xe00001, shogwarr_oki_bank_w                    },    // Samples Bankswitching
  683.     { -1 }
  684. };
  685.  
  686.  
  687.  
  688.  
  689. /***************************************************************************
  690.  
  691.                                 Input Ports
  692.  
  693. ***************************************************************************/
  694.  
  695.  
  696.  
  697. /***************************************************************************
  698.                         [ The Berlin Wall (set 1) ]
  699. ***************************************************************************/
  700.  
  701. //    Input Ports:    [0] Joy 1            [1] Joy 2
  702. //                    [2] Coins            [3] ?
  703. //                    [4] DSW    1            [5] DSW 2
  704.  
  705. INPUT_PORTS_START( berlwall )
  706.  
  707.     PORT_START    // IN0 - Player 1 - 680000.w
  708.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  709.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  710.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  711.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  712.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  713.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  714.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
  715.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  716.  
  717.     PORT_START    // IN1 - Player 2 - 680002.w
  718.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  719.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  720.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  721.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  722.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  723.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  724.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
  725.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  726.  
  727.     PORT_START    // IN2 - Coins - 680004.w
  728.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_START1    )
  729.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_START2    )
  730.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_COIN1        )
  731.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_COIN2        )
  732.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_SERVICE    )    // test
  733.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_TILT        )
  734.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_COIN3        )    // operator's facility
  735.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN    )
  736.  
  737.     PORT_START    // IN3 - ? - 680006.w
  738.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
  739.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
  740.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
  741.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
  742.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  743.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  744.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  745.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  746.  
  747.     PORT_START    // IN4 - DSW 1 - $200018.b <- ! $80001d.b
  748.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
  749.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  750.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  751.     PORT_DIPNAME( 0x02, 0x02, "Reserved" )
  752.     PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
  753.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  754.     PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) )
  755.     PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
  756.     PORT_DIPSETTING(    0x04, DEF_STR( 3C_1C ) )
  757.     PORT_DIPSETTING(    0x0c, DEF_STR( 2C_1C ) )
  758.     PORT_DIPSETTING(    0x1c, DEF_STR( 1C_1C ) )
  759.     PORT_DIPSETTING(    0x08, DEF_STR( 2C_3C ) )
  760.     PORT_DIPSETTING(    0x18, DEF_STR( 1C_2C ) )
  761.     PORT_DIPSETTING(    0x14, DEF_STR( 1C_3C ) )
  762.     PORT_DIPSETTING(    0x10, DEF_STR( 1C_4C ) )
  763.     PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Coin_B ) )
  764.     PORT_DIPSETTING(    0x60, DEF_STR( 2C_1C ) )
  765.     PORT_DIPSETTING(    0xe0, DEF_STR( 1C_1C ) )
  766.     PORT_DIPSETTING(    0x40, DEF_STR( 2C_3C ) )
  767.     PORT_DIPSETTING(    0xc0, DEF_STR( 1C_2C ) )
  768.     PORT_DIPSETTING(    0xa0, DEF_STR( 1C_3C ) )
  769.     PORT_DIPSETTING(    0x80, DEF_STR( 1C_4C ) )
  770.     PORT_DIPSETTING(    0x20, DEF_STR( 1C_5C ) )
  771.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_6C ) )
  772.  
  773.     PORT_START    // IN5 - DSW 2 - $200019.b <- $80001f.b
  774.     PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
  775.     PORT_DIPSETTING(    0x02, "Easy"    )
  776.     PORT_DIPSETTING(    0x03, "Normal"  )
  777.     PORT_DIPSETTING(    0x01, "Hard"    )
  778.     PORT_DIPSETTING(    0x00, "Hardest" )
  779.     PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )    // 1p lives at 202982.b
  780.     PORT_DIPSETTING(    0x00, "1" )
  781.     PORT_DIPSETTING(    0x0c, "2" )
  782.     PORT_DIPSETTING(    0x08, "3" )
  783.     PORT_DIPSETTING(    0x04, "5" )
  784.     PORT_DIPNAME( 0x30, 0x30, "Country"   )
  785.     PORT_DIPSETTING(    0x30, "England" )
  786.     PORT_DIPSETTING(    0x20, "Italy"   )
  787.     PORT_DIPSETTING(    0x10, "Germany" )
  788.     PORT_DIPSETTING(    0x00, "Freeze Screen" )
  789.     PORT_DIPNAME( 0x40, 0x40, DEF_STR( Demo_Sounds ) )
  790.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  791.     PORT_DIPSETTING(    0x40, DEF_STR( On ) )
  792.     PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
  793.  
  794. INPUT_PORTS_END
  795.  
  796.  
  797.  
  798. /***************************************************************************
  799.                         [ The Berlin Wall (set 2) ]
  800. ***************************************************************************/
  801.  
  802. //    Same as berlwall, but for a different lives setting
  803. //
  804. //    Input Ports:    [0] Joy 1            [1] Joy 2
  805. //                    [2] Coins            [3] ?
  806. //                    [4] DSW    1            [5] DSW 2
  807.  
  808. INPUT_PORTS_START( berlwalt )
  809.  
  810.     PORT_START    // IN0 - Player 1 - 680000.w
  811.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  812.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  813.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  814.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  815.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  816.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  817.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
  818.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  819.  
  820.     PORT_START    // IN1 - Player 2 - 680002.w
  821.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  822.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  823.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  824.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  825.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  826.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  827.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
  828.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  829.  
  830.     PORT_START    // IN2 - Coins - 680004.w
  831.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_START1    )
  832.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_START2    )
  833.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_COIN1        )
  834.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_COIN2        )
  835.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_SERVICE    )    // test
  836.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_TILT        )
  837.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_COIN3        )    // operator's facility
  838.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN    )
  839.  
  840.     PORT_START    // IN3 - ? - 680006.w
  841.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
  842.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
  843.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
  844.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
  845.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  846.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  847.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  848.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  849.  
  850.     PORT_START    // IN4 - DSW 1 - $80001d.b
  851.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
  852.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  853.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  854.     PORT_DIPNAME( 0x02, 0x02, "Reserved" )
  855.     PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
  856.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  857.     PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) )
  858.     PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
  859.     PORT_DIPSETTING(    0x04, DEF_STR( 3C_1C ) )
  860.     PORT_DIPSETTING(    0x0c, DEF_STR( 2C_1C ) )
  861.     PORT_DIPSETTING(    0x1c, DEF_STR( 1C_1C ) )
  862.     PORT_DIPSETTING(    0x08, DEF_STR( 2C_3C ) )
  863.     PORT_DIPSETTING(    0x18, DEF_STR( 1C_2C ) )
  864.     PORT_DIPSETTING(    0x14, DEF_STR( 1C_3C ) )
  865.     PORT_DIPSETTING(    0x10, DEF_STR( 1C_4C ) )
  866.     PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Coin_B ) )
  867.     PORT_DIPSETTING(    0x60, DEF_STR( 2C_1C ) )
  868.     PORT_DIPSETTING(    0xe0, DEF_STR( 1C_1C ) )
  869.     PORT_DIPSETTING(    0x40, DEF_STR( 2C_3C ) )
  870.     PORT_DIPSETTING(    0xc0, DEF_STR( 1C_2C ) )
  871.     PORT_DIPSETTING(    0xa0, DEF_STR( 1C_3C ) )
  872.     PORT_DIPSETTING(    0x80, DEF_STR( 1C_4C ) )
  873.     PORT_DIPSETTING(    0x20, DEF_STR( 1C_5C ) )
  874.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_6C ) )
  875.  
  876.     PORT_START    // IN5 - DSW 2 - $80001f.b
  877.     PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
  878.     PORT_DIPSETTING(    0x02, "Easy"    )
  879.     PORT_DIPSETTING(    0x03, "Normal"  )
  880.     PORT_DIPSETTING(    0x01, "Hard"    )
  881.     PORT_DIPSETTING(    0x00, "Hardest" )
  882.     PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )
  883.     PORT_DIPSETTING(    0x00, "7" )
  884.     PORT_DIPSETTING(    0x04, "5" )
  885.     PORT_DIPSETTING(    0x0c, "3" )
  886.     PORT_DIPSETTING(    0x08, "2" )
  887.     PORT_DIPNAME( 0x30, 0x30, "Country"   )
  888.     PORT_DIPSETTING(    0x30, "England" )
  889.     PORT_DIPSETTING(    0x20, "Italy"   )
  890.     PORT_DIPSETTING(    0x10, "Germany" )
  891.     PORT_DIPSETTING(    0x00, "Freeze Screen" )
  892.     PORT_DIPNAME( 0x40, 0x40, DEF_STR( Demo_Sounds ) )
  893.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  894.     PORT_DIPSETTING(    0x40, DEF_STR( On ) )
  895.     PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
  896.  
  897. INPUT_PORTS_END
  898.  
  899.  
  900.  
  901. /***************************************************************************
  902.                         [ Great 1000 Miles Rally ]
  903. ***************************************************************************/
  904.  
  905. //    Input Ports:    [0] Joy 1            [1] Joy 2
  906. //                    [2] Coins            [3] ?
  907. //                    [4] DSW                [5] Driving Wheel
  908.  
  909. INPUT_PORTS_START( gtmr )
  910.  
  911.     PORT_START    // IN0 - Player 1 - b00000.w
  912.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  913.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  914.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  915.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  916.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 ) // swapped for consistency:
  917.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 ) // button1 is usually accel.
  918.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  919.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  920.  
  921.     PORT_START    // IN1 - Player 2 - b00002.w
  922.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  923.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  924.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  925.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  926.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 ) // swapped for consistency:
  927.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 ) // button1 is usually accel.
  928.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  929.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  930.  
  931.     PORT_START    // IN2 - Coins - b00004.w
  932.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_START1    )
  933.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_START2    )
  934.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_COIN1        )
  935.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_COIN2        )
  936.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_SERVICE    )    // test
  937.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_TILT        )
  938.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_COIN3        )    // operator's facility
  939.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN    )
  940.  
  941.     PORT_START    // IN3 - Seems unused ! - b00006.w
  942.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
  943.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
  944.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
  945.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
  946.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  947.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  948.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  949.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  950.  
  951.     PORT_START    // IN4 - DSW from the MCU - 101265.b <- 206000.b
  952.     PORT_SERVICE( 0x0100, IP_ACTIVE_LOW )
  953.     PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Flip_Screen ) )
  954.     PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
  955.     PORT_DIPSETTING(      0x0000, DEF_STR( On )  )
  956.     PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Cabinet )  )
  957.     PORT_DIPSETTING(      0x0400, DEF_STR( Upright )  )
  958.     PORT_DIPSETTING(      0x0000, DEF_STR( Cocktail ) )
  959.     PORT_DIPNAME( 0x1800, 0x1800, "Controls"    )
  960.     PORT_DIPSETTING(      0x1800, "1 Joystick"  )
  961.     PORT_DIPSETTING(      0x0800, "2 Joysticks" )
  962.     PORT_DIPSETTING(      0x1000, "Wheel (360)" )
  963.     PORT_DIPSETTING(      0x0000, "Wheel (270)" )
  964.     PORT_DIPNAME( 0x2000, 0x2000, "Use Brake"    )
  965.     PORT_DIPSETTING(      0x0000, DEF_STR( Off ) )
  966.     PORT_DIPSETTING(      0x2000, DEF_STR( On )  )
  967.     PORT_DIPNAME( 0xc000, 0xc000, "National Anthem & Flag" )
  968.     PORT_DIPSETTING(      0xc000, "Use Memory"  )
  969.     PORT_DIPSETTING(      0x8000, "Anthem Only" )
  970.     PORT_DIPSETTING(      0x4000, "Flag Only"   )
  971.     PORT_DIPSETTING(      0x0000, "None"        )
  972.  
  973.     PORT_START    // IN5 - Wheel - 100015.b <- ffffe.b
  974.     PORT_ANALOG ( 0x00ff, 0x0080, IPT_AD_STICK_X | IPF_CENTER, 30, 1, 0x00, 0xff )
  975.  
  976. INPUT_PORTS_END
  977.  
  978.  
  979.  
  980.  
  981.  
  982. /***************************************************************************
  983.                             [ Shogun Warriors ]
  984. ***************************************************************************/
  985.  
  986. //    Input Ports:    [0] Joy 1            [1] Joy 2
  987. //                    [2] Coins            [3] ?
  988. //                    [4] DSW
  989.  
  990. INPUT_PORTS_START( shogwarr )
  991.  
  992.     PORT_START    // IN0 - - b80000.w
  993.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  994.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  995.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  996.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  997.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  998.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  999.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
  1000.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )    // ? tested
  1001.  
  1002.     PORT_START    // IN1 - - b80002.w
  1003.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  1004.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  1005.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  1006.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  1007.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  1008.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  1009.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
  1010.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )    // ? tested
  1011.  
  1012.     PORT_START    // IN2 - Coins - b80004.w
  1013.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_START1    )
  1014.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_START2    )
  1015.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_COIN1        )
  1016.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_COIN2        )
  1017.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_SERVICE    )    // test
  1018.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_TILT        )
  1019.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_COIN3        )    // operator's facility
  1020.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN    )    // ? tested
  1021.  
  1022.     PORT_START    // IN3 - ? - b80006.w
  1023.     PORT_BIT(  0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1024.     PORT_BIT(  0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1025.     PORT_BIT(  0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1026.     PORT_BIT(  0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1027.     PORT_BIT(  0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1028.     PORT_BIT(  0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1029.     PORT_BIT(  0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1030.     PORT_BIT(  0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
  1031.  
  1032.     PORT_START    // IN4 - DSW from the MCU - 102e15.b <- 200059.b
  1033.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
  1034.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  1035.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  1036.     PORT_SERVICE( 0x02, IP_ACTIVE_LOW )
  1037.     PORT_DIPNAME( 0x04, 0x04, DEF_STR( Demo_Sounds ) )
  1038.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  1039.     PORT_DIPSETTING(    0x04, DEF_STR( On ) )
  1040.     PORT_DIPNAME( 0x38, 0x38, DEF_STR( Difficulty ) )
  1041.     PORT_DIPSETTING(    0x38, "1" )    // easy
  1042.     PORT_DIPSETTING(    0x30, "2" )
  1043.     PORT_DIPSETTING(    0x28, "3" )
  1044.     PORT_DIPSETTING(    0x20, "4" )
  1045.     PORT_DIPSETTING(    0x18, "5" )
  1046.     PORT_DIPSETTING(    0x10, "6" )
  1047.     PORT_DIPSETTING(    0x08, "7" )
  1048.     PORT_DIPSETTING(    0x00, "8" )
  1049.     PORT_DIPNAME( 0x40, 0x40, "Can Join During Game" )
  1050.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )    //    2 credits        winner vs computer
  1051.     PORT_DIPSETTING(    0x40, DEF_STR( On ) )    //    1 credit        game over
  1052.     PORT_DIPNAME( 0x80, 0x80, "Special Continue Mode" )
  1053.     PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
  1054.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  1055.  
  1056. INPUT_PORTS_END
  1057.  
  1058.  
  1059.  
  1060.  
  1061.  
  1062.  
  1063. /***************************************************************************
  1064.  
  1065.                                 Graphics Layouts
  1066.  
  1067. ***************************************************************************/
  1068.  
  1069.  
  1070. /*
  1071.     16x16x4 made of 4 8x8x4 blocks arrenged like:             01
  1072.      (nibbles are swapped for tiles, not for sprites)        23
  1073. */
  1074. #define LAYOUT_16x16x4(_name_,_romsize_) \
  1075. static struct GfxLayout _name_ =\
  1076. {\
  1077.     16,16,\
  1078.     (_romsize_)*8/(16*16*4),\
  1079.     4,\
  1080.     {0, 1, 2, 3},\
  1081.     {0*4,1*4,2*4,3*4,4*4,5*4,6*4,7*4, \
  1082.      0*4+32*8,1*4+32*8,2*4+32*8,3*4+32*8,4*4+32*8,5*4+32*8,6*4+32*8,7*4+32*8}, \
  1083.     {0*32,1*32,2*32,3*32,4*32,5*32,6*32,7*32,\
  1084.      0*32+32*16,1*32+32*16,2*32+32*16,3*32+32*16,4*32+32*16,5*32+32*16,6*32+32*16,7*32+32*16},\
  1085.     16*16*4\
  1086. };
  1087.  
  1088.  
  1089. /*
  1090.     16x16x8 made of 4 8x8x8 blocks arrenged like:    01
  1091.                                                     23
  1092. */
  1093. #define LAYOUT_16x16x8(_name_,_romsize_) \
  1094. static struct GfxLayout _name_ =\
  1095. {\
  1096.     16,16,\
  1097.     (_romsize_)*8/(16*16*8),\
  1098.     8,\
  1099.     {0, 1, 2, 3, 4, 5, 6, 7},\
  1100.     {0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8, \
  1101.      0*8+64*8,1*8+64*8,2*8+64*8,3*8+64*8,4*8+64*8,5*8+64*8,6*8+64*8,7*8+64*8}, \
  1102.     {0*64,1*64,2*64,3*64,4*64,5*64,6*64,7*64,\
  1103.      0*64+64*16,1*64+64*16,2*64+64*16,3*64+64*16,4*64+64*16,5*64+64*16,6*64+64*16,7*64+64*16},\
  1104.     16*16*8\
  1105. };
  1106.  
  1107.  
  1108. LAYOUT_16x16x8(layout_8bit_8M,   0x800000)
  1109.  
  1110. LAYOUT_16x16x4(layout_4bit_HM,   0x080000)
  1111. LAYOUT_16x16x4(layout_4bit_2M,   0x200000)
  1112. LAYOUT_16x16x4(layout_4bit_4M,   0x400000)
  1113. LAYOUT_16x16x4(layout_4bit_6M,   0x500000)
  1114.  
  1115.  
  1116. /***************************************************************************
  1117.                             [ The Berlin Wall ]
  1118. ***************************************************************************/
  1119.  
  1120. LAYOUT_16x16x4(layout_4bit_1_2M,   0x120000)
  1121.  
  1122. static struct GfxDecodeInfo berlwall_gfxdecodeinfo[] =
  1123. {
  1124.     { REGION_GFX1, 0, &layout_4bit_HM,        0x40 * 16,    0x40 }, // [0] Layers
  1125.     { REGION_GFX2, 0, &layout_4bit_1_2M,    0,            0x40 }, // [1] Sprites
  1126.     { -1 }
  1127. };
  1128.  
  1129. /***************************************************************************
  1130.                         [ Great 1000 Miles Rally ]
  1131. ***************************************************************************/
  1132.  
  1133. static struct GfxDecodeInfo gtmr_gfxdecodeinfo[] =
  1134. {
  1135.     { REGION_GFX1, 0, &layout_4bit_2M,    0,            0x40 }, // [0] Layers
  1136.     { REGION_GFX2, 0, &layout_8bit_8M,    0x40 * 256,    0x40 }, // [1] Sprites
  1137.     { -1 }
  1138. };
  1139.  
  1140. /***************************************************************************
  1141.                             [ Shogun Warriors ]
  1142. ***************************************************************************/
  1143.  
  1144. static struct GfxDecodeInfo shogwarr_gfxdecodeinfo[] =
  1145. {
  1146.     { REGION_GFX1, 0, &layout_4bit_4M,    0x40 * 16,    0x40 }, // [0] Layers
  1147.     { REGION_GFX2, 0, &layout_4bit_6M,    0,            0x40 }, // [1] Sprites
  1148.     { -1 }
  1149. };
  1150.  
  1151.  
  1152.  
  1153. /***************************************************************************
  1154.  
  1155.                                 Machine Drivers
  1156.  
  1157. ***************************************************************************/
  1158.  
  1159.  
  1160.  
  1161. /***************************************************************************
  1162.                             [ The Berlin Wall ]
  1163. ***************************************************************************/
  1164.  
  1165. static struct OKIM6295interface berlwall_okim6295_interface =
  1166. {
  1167.     1,
  1168.     { 8000 },        /* ? */
  1169.     { REGION_SOUND1 },
  1170.     { 40 }
  1171. };
  1172.  
  1173. static struct AY8910interface berlwall_ay8910_interface =
  1174. {
  1175.     2,
  1176.     1000000,    /* ? */
  1177.     { MIXERG(30,MIXER_GAIN_2x,MIXER_PAN_LEFT), MIXERG(30,MIXER_GAIN_2x,MIXER_PAN_RIGHT) },
  1178.     { input_port_4_r, 0 },    /* input A: DSW 1 */
  1179.     { input_port_5_r, 0 },    /* input B: DSW 2 */
  1180.     { 0, 0 },
  1181.     { 0, 0 }
  1182. };
  1183.  
  1184.  
  1185. /*
  1186.     1-3] e8c:
  1187.     4]   e54:
  1188.     5]   de4:
  1189.     6-7] rte
  1190. */
  1191. #define BERLWALL_INTERRUPTS_NUM    3
  1192. int berlwall_interrupt(void)
  1193. {
  1194.     switch ( cpu_getiloops() )
  1195.     {
  1196.         case 2:  return 3;
  1197.         case 1:  return 4;
  1198.         case 0:  return 5;
  1199.         default: return 0;
  1200.     }
  1201. }
  1202.  
  1203.  
  1204. static struct MachineDriver machine_driver_berlwall =
  1205. {
  1206.     {
  1207.         {
  1208.             CPU_M68000,
  1209.             12000000,    /* like shogwarr? */
  1210.             berlwall_readmem,berlwall_writemem,0,0,
  1211.             berlwall_interrupt, BERLWALL_INTERRUPTS_NUM
  1212.         }
  1213.     },
  1214.     60, DEFAULT_REAL_60HZ_VBLANK_DURATION,
  1215.     1,
  1216.     berlwall_init_machine,
  1217.  
  1218.     /* video hardware */
  1219.     256, 256, { 0, 256-1, 0 + 16, 256 -1 - 16},
  1220.     berlwall_gfxdecodeinfo,
  1221.     0x1000 / 2 + 32768, 0x1000 / 2,    /* 32768 static colors for the bg */
  1222.     berlwall_init_palette,
  1223.     VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE  | VIDEO_UPDATE_AFTER_VBLANK,    // mangled sprites otherwise
  1224.     0,
  1225.     berlwall_vh_start,
  1226.     berlwall_vh_stop,
  1227.     kaneko16_vh_screenrefresh,
  1228.  
  1229.     /* sound hardware */
  1230.     SOUND_SUPPORTS_STEREO,0,0,0,
  1231.     {
  1232.         {
  1233.             SOUND_AY8910,
  1234.             &berlwall_ay8910_interface
  1235.         },
  1236.         {
  1237.             SOUND_OKIM6295,
  1238.             &berlwall_okim6295_interface
  1239.         }
  1240.     }
  1241. };
  1242.  
  1243.  
  1244.  
  1245.  
  1246. /***************************************************************************
  1247.                         [ Great 1000 Miles Rally ]
  1248. ***************************************************************************/
  1249.  
  1250. static struct OKIM6295interface gtmr_okim6295_interface =
  1251. {
  1252.     2,
  1253.     {12000,12000},    /* ? everything seems synced, using 12KHz */
  1254.     { REGION_SOUND1, REGION_SOUND2 },
  1255.     { 50, 50 }
  1256. };
  1257.  
  1258. /*
  1259.     3] 476:            time, input ports, scroll registers
  1260.     4] 466->258e:    set sprite ram
  1261.     5] 438:            set sprite colors
  1262.  
  1263.     VIDEO_UPDATE_AFTER_VBLANK fixes the mangled/wrong colored sprites
  1264. */
  1265. #define GTMR_INTERRUPTS_NUM    3
  1266. int gtmr_interrupt(void)
  1267. {
  1268.     switch ( cpu_getiloops() )
  1269.     {
  1270.         case 2:  return 3;
  1271.         case 1:  return 4;
  1272.         case 0:  return 5;
  1273.         default: return 0;
  1274.     }
  1275. }
  1276.  
  1277. static struct MachineDriver machine_driver_gtmr =
  1278. {
  1279.     {
  1280.         {
  1281.             CPU_M68000,
  1282.             16000000,    /* ? Most likely a 68000-HC16 */
  1283.             gtmr_readmem,gtmr_writemem,0,0,
  1284.             gtmr_interrupt, GTMR_INTERRUPTS_NUM
  1285.         }
  1286.     },
  1287.     60, DEFAULT_REAL_60HZ_VBLANK_DURATION,
  1288.     1,
  1289.     gtmr_init_machine,
  1290.  
  1291.     /* video hardware */
  1292.     320, 240, { 0, 320-1, 0, 240-1 },
  1293.     gtmr_gfxdecodeinfo,
  1294.     0x10000 / 2, 0x10000 / 2,
  1295.     0,
  1296.     VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE | VIDEO_UPDATE_AFTER_VBLANK,
  1297.     0,
  1298.     kaneko16_vh_start,
  1299.     0,
  1300.     kaneko16_vh_screenrefresh,
  1301.  
  1302.     /* sound hardware */
  1303.     0,0,0,0,
  1304.     {
  1305.         {
  1306.             SOUND_OKIM6295,
  1307.             >mr_okim6295_interface
  1308.         }
  1309.     }
  1310. };
  1311.  
  1312.  
  1313.  
  1314.  
  1315.  
  1316.  
  1317.  
  1318. /***************************************************************************
  1319.                             [ Shogun Warriors ]
  1320. ***************************************************************************/
  1321.  
  1322. static struct OKIM6295interface shogwarr_okim6295_interface =
  1323. {
  1324.     2,
  1325.     {12000,12000},        /* ? */
  1326.     { REGION_SOUND1, REGION_SOUND2 },
  1327.     { 50, 50 }
  1328. };
  1329.  
  1330.  
  1331. /*
  1332.     2] 100:    rte
  1333.     3] 102:
  1334.     4] 136:
  1335.         movem.l D0-D7/A0-A6, -(A7)
  1336.         movea.l $207808.l, A0    ; from mcu?
  1337.         jmp     ($4,A0)
  1338.  
  1339.     other: busy loop
  1340. */
  1341. #define SHOGWARR_INTERRUPTS_NUM    3
  1342. int shogwarr_interrupt(void)
  1343. {
  1344.     switch ( cpu_getiloops() )
  1345.     {
  1346.         case 2:  return 2;
  1347.         case 1:  return 3;
  1348. //        case 0:  return 4;
  1349.         default: return 0;
  1350.     }
  1351. }
  1352.  
  1353. static struct MachineDriver machine_driver_shogwarr =
  1354. {
  1355.     {
  1356.         {
  1357.             CPU_M68000,
  1358.             12000000,
  1359.             shogwarr_readmem,shogwarr_writemem,0,0,
  1360.             shogwarr_interrupt, SHOGWARR_INTERRUPTS_NUM
  1361.         }
  1362.     },
  1363.     60,DEFAULT_60HZ_VBLANK_DURATION,
  1364.     1,
  1365.     shogwarr_init_machine,
  1366.  
  1367.     /* video hardware */
  1368.     320, 240, { 0, 320-1, 0, 240-1 },
  1369.     shogwarr_gfxdecodeinfo,
  1370.     0x1000 / 2, 0x1000 / 2,
  1371.     0,
  1372.     VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE,
  1373.     0,
  1374.     kaneko16_vh_start,
  1375.     0,
  1376.     kaneko16_vh_screenrefresh,
  1377.  
  1378.     /* sound hardware */
  1379.     0,0,0,0,
  1380.     {
  1381.         {
  1382.             SOUND_OKIM6295,
  1383.             &shogwarr_okim6295_interface
  1384.         }
  1385.     }
  1386. };
  1387.  
  1388.  
  1389.  
  1390.  
  1391. /***************************************************************************
  1392.  
  1393.                                 ROMs Loading
  1394.  
  1395. ***************************************************************************/
  1396.  
  1397.  
  1398. /*
  1399.  Sprites and tiles are stored in the ROMs using the same layout. But tiles
  1400.  have the even and odd pixels swapped. So we use this function to untangle
  1401.  them and have one single gfxlayout for both tiles and sprites.
  1402. */
  1403. void kaneko16_unscramble_tiles(int region)
  1404. {
  1405.     unsigned char *RAM    =    memory_region(region);
  1406.     int size            =    memory_region_length(region);
  1407.     int i;
  1408.  
  1409.     for (i = 0; i < size; i ++)
  1410.     {
  1411.         RAM[i] = ((RAM[i] & 0xF0)>>4) + ((RAM[i] & 0x0F)<<4);
  1412.     }
  1413. }
  1414.  
  1415. void init_kaneko16(void)
  1416. {
  1417.     kaneko16_unscramble_tiles(REGION_GFX1);
  1418. }
  1419.  
  1420.  
  1421. /***************************************************************************
  1422.  
  1423.                             [ The Berlin Wall ]
  1424.  
  1425. The Berlin Wall, Kaneko 1991, BW-002
  1426.  
  1427. ----
  1428.  
  1429. BW-004 BW-008                    VU-003
  1430. BW-005 BW-009                    VU-003
  1431. BW-006 BW-00A                    VU-003
  1432. BW-007 BW-00B                          6116-90
  1433.                                        6116-90
  1434. BW-003                           52256  52256
  1435.                                  BW101A BW100A
  1436. 5864
  1437. 5864                   MUX2      68000
  1438.             VIEW2
  1439. BW300
  1440. BW-002
  1441. BW-001                      42101
  1442.                             42101
  1443. 41464 41464      VU-002
  1444. 41464 41464                      YM2149  IU-004
  1445. 41464 41464                      YM2149
  1446.                            SWB             BW-000  6295
  1447.                            SWA
  1448.  
  1449.  
  1450. ***************************************************************************/
  1451.  
  1452. ROM_START( berlwall )
  1453.  
  1454.      ROM_REGION( 0x040000, REGION_CPU1 )            /* 68000 Code */
  1455.     ROM_LOAD_EVEN( "bw100a", 0x000000, 0x020000, 0xe6bcb4eb )
  1456.     ROM_LOAD_ODD(  "bw101a", 0x000000, 0x020000, 0x38056fb2 )
  1457.  
  1458.     ROM_REGION( 0x080000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (Scrambled) */
  1459.     ROM_LOAD( "bw003",  0x000000, 0x080000, 0xfbb4b72d )
  1460.  
  1461.     ROM_REGION( 0x120000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1462.     ROM_LOAD( "bw001",  0x000000, 0x080000, 0xbc927260 )
  1463.     ROM_LOAD( "bw002",  0x080000, 0x080000, 0x223f5465 )
  1464.     ROM_LOAD( "bw300",  0x100000, 0x020000, 0xb258737a )
  1465.  
  1466.     ROM_REGION( 0x400000, REGION_GFX3 | REGIONFLAG_DISPOSE )    /* High Color Background */
  1467.     ROM_LOAD_GFX_EVEN( "bw004",  0x000000, 0x080000, 0x5300c34d )
  1468.     ROM_LOAD_GFX_ODD(  "bw008",  0x000000, 0x080000, 0x9aaf2f2f ) // FIXED BITS (xxxxxxx0)
  1469.     ROM_LOAD_GFX_EVEN( "bw005",  0x100000, 0x080000, 0x16db6d43 )
  1470.     ROM_LOAD_GFX_ODD(  "bw009",  0x100000, 0x080000, 0x1151a0b0 ) // FIXED BITS (xxxxxxx0)
  1471.     ROM_LOAD_GFX_EVEN( "bw006",  0x200000, 0x080000, 0x73a35d1f )
  1472.     ROM_LOAD_GFX_ODD(  "bw00a",  0x200000, 0x080000, 0xf447dfc2 ) // FIXED BITS (xxxxxxx0)
  1473.     ROM_LOAD_GFX_EVEN( "bw007",  0x300000, 0x080000, 0x97f85c87 )
  1474.     ROM_LOAD_GFX_ODD(  "bw00b",  0x300000, 0x080000, 0xb0a48225 ) // FIXED BITS (xxxxxxx0)
  1475.  
  1476.     ROM_REGION( 0x040000, REGION_SOUND1 )    /* Samples */
  1477.     ROM_LOAD( "bw000",  0x000000, 0x040000, 0xd8fe869d )
  1478.  
  1479. ROM_END
  1480.  
  1481.  
  1482.  
  1483.  
  1484. ROM_START( berlwalt )
  1485.  
  1486.      ROM_REGION( 0x040000, REGION_CPU1 )            /* 68000 Code */
  1487.     ROM_LOAD_EVEN( "u23_01.bin", 0x000000, 0x020000, 0x76b526ce )
  1488.     ROM_LOAD_ODD(  "u39_01.bin", 0x000000, 0x020000, 0x78fa7ef2 )
  1489.  
  1490.     ROM_REGION( 0x080000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (Scrambled) */
  1491.     ROM_LOAD( "bw003",  0x000000, 0x080000, 0xfbb4b72d )
  1492.  
  1493.     ROM_REGION( 0x120000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1494.     ROM_LOAD( "bw001",  0x000000, 0x080000, 0xbc927260 )
  1495.     ROM_LOAD( "bw002",  0x080000, 0x080000, 0x223f5465 )
  1496.     ROM_LOAD( "bw300",  0x100000, 0x020000, 0xb258737a )
  1497.  
  1498.     ROM_REGION( 0x400000, REGION_GFX3 | REGIONFLAG_DISPOSE )    /* High Color Background */
  1499.     ROM_LOAD_GFX_EVEN( "bw004",  0x000000, 0x080000, 0x5300c34d )
  1500.     ROM_LOAD_GFX_ODD(  "bw008",  0x000000, 0x080000, 0x9aaf2f2f ) // FIXED BITS (xxxxxxx0)
  1501.     ROM_LOAD_GFX_EVEN( "bw005",  0x100000, 0x080000, 0x16db6d43 )
  1502.     ROM_LOAD_GFX_ODD(  "bw009",  0x100000, 0x080000, 0x1151a0b0 ) // FIXED BITS (xxxxxxx0)
  1503.     ROM_LOAD_GFX_EVEN( "bw006",  0x200000, 0x080000, 0x73a35d1f )
  1504.     ROM_LOAD_GFX_ODD(  "bw00a",  0x200000, 0x080000, 0xf447dfc2 ) // FIXED BITS (xxxxxxx0)
  1505.     ROM_LOAD_GFX_EVEN( "bw007",  0x300000, 0x080000, 0x97f85c87 )
  1506.     ROM_LOAD_GFX_ODD(  "bw00b",  0x300000, 0x080000, 0xb0a48225 ) // FIXED BITS (xxxxxxx0)
  1507.  
  1508.     ROM_REGION( 0x040000, REGION_SOUND1 )    /* Samples */
  1509.     ROM_LOAD( "bw000",  0x000000, 0x040000, 0xd8fe869d )
  1510.  
  1511. ROM_END
  1512.  
  1513.  
  1514.  
  1515.  
  1516. /***************************************************************************
  1517.  
  1518.                         [ Great 1000 Miles Rally ]
  1519.  
  1520. GMMU2+1    512K * 2    68k
  1521. GMMU23    1M        OKI6295: 00000-2ffff + chunks of 0x10000 with headers
  1522. GMMU24    1M        OKI6295: chunks of 0x40000 with headers - FIRST AND SECOND HALF IDENTICAL
  1523.  
  1524. GMMU27    2M        sprites
  1525. GMMU28    2M        sprites
  1526. GMMU29    2M        sprites
  1527. GMMU30    512k    sprites
  1528.  
  1529. GMMU64    1M        sprites - FIRST AND SECOND HALF IDENTICAL
  1530. GMMU65    1M        sprites - FIRST AND SECOND HALF IDENTICAL
  1531.  
  1532. GMMU52    2M        tiles
  1533.  
  1534.  
  1535. ---------------------------------------------------------------------------
  1536.                                 Game code
  1537. ---------------------------------------------------------------------------
  1538.  
  1539. 100000.b    <- (!b00000.b) & 7f    [1p]
  1540.     01.b    previous value of the above
  1541.     02.b    bits gone high
  1542.  
  1543. 100008.b    <- (!b00002.b) & 7f    [2p]
  1544.  
  1545. 100010.b    <- !b00004.b [coins]
  1546.     11.b    previous value of the above
  1547.     12.b    bits gone high
  1548.  
  1549. 100013.b    <- b00006.b    (both never accessed again?)
  1550.  
  1551. 100015.b    <- wheel value
  1552.  
  1553. 600000.w    <- 100a20.w + 100a30.w        600002.w    <- 100a22.w + 100a32.w
  1554. 600004.w    <- 100a24.w + 100a34.w        600006.w    <- 100a26.w + 100a36.w
  1555.  
  1556. 680000.w    <- 100a28.w + 100a38.w        680002.w    <- 100a2a.w + 100a3a.w
  1557. 680004.w    <- 100a2c.w + 100a3c.w        680006.w    <- 100a2e.w + 100a3e.w
  1558.  
  1559. 101265.b    <- DSW (from 206000)
  1560. 101266        <- Settings from NVRAM (0x80 bytes from 208000)
  1561.  
  1562. 1034f8.b    credits
  1563. 103502.b    coins x ..
  1564. 103503.b    .. credits
  1565.  
  1566. 1035ec.l    *** Time (BCD: seconds * 10000) ***
  1567. 103e64.w    *** Speed << 4 ***
  1568.  
  1569. 10421a.b    bank for the oki mapped at 800000
  1570. 104216.b    last value of the above
  1571.  
  1572. 10421c.b    bank for the oki mapped at 880000
  1573. 104218.b    last value of the above
  1574.  
  1575. ROUTINES:
  1576.  
  1577. dd6    print string: a2->scr ; a1->string ; d1.l = xpos.w<<6|ypos.w<<6
  1578.  
  1579. Trap #2 = 43a0 ; d0.w = routine index ; (where not specified: 43c0):
  1580. 1:  43C4    2:  43F8    3:  448E    4:  44EE
  1581. 5:  44D2    6:  4508    7:  453A    10: 0AF6
  1582. 18: 4580    19: 4604
  1583. 20> 2128    writes 700000-70001f
  1584. 21: 21F6
  1585. 24> 2346    clears 400000-401407 (641*8 = $281*8)
  1586. 30> 282A    writes 600008/9/b/e-f, 680008/9/b/e-f
  1587. 31: 295A
  1588. 32> 2B36    100a30-f <- 100a10-f
  1589. 34> 2B4C    clears 500000-503fff, 580000-583fff
  1590. 35> 2B9E    d1.w = selects between:    500000;501000;580000;581000.
  1591.             Fill 0x1000 bytes from there with d2.l
  1592.  
  1593. 70: 2BCE>    11d8a
  1594. 71: 2BD6
  1595. 74: 2BDE    90: 3D44
  1596. 91> 3D4C    wait for bit 0 of d00000 to be 0
  1597. 92> 3D5C    200010.w<-D1    200012.w<-D2    200014.w<-D3
  1598. f1: 10F6
  1599.  
  1600.  
  1601. ***************************************************************************/
  1602.  
  1603. /*    This version displays:
  1604.  
  1605.     tb05mm-eu "1000 miglia"
  1606.     master up= 94/07/18 15:12:35            */
  1607.  
  1608. ROM_START( gtmr )
  1609.  
  1610.      ROM_REGION( 0x100000, REGION_CPU1 )            /* 68000 Code */
  1611.     ROM_LOAD_EVEN( "u2.bin", 0x000000, 0x080000, 0x031799f7 )
  1612.     ROM_LOAD_ODD(  "u1.bin", 0x000000, 0x080000, 0x6238790a )
  1613.  
  1614.      ROM_REGION( 0x010000, REGION_CPU2 )            /* MCU Code */
  1615.     ROM_LOAD( "mcu_code",  0x000000, 0x010000, 0x00000000 )
  1616.  
  1617.     ROM_REGION( 0x200000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (scrambled) */
  1618.     ROM_LOAD( "gmmu52.bin",  0x000000, 0x200000, 0xb15f6b7f )
  1619.  
  1620.     ROM_REGION( 0x900000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1621.     ROM_LOAD( "gmmu27.bin",  0x000000, 0x200000, 0xc0ab3efc )
  1622.     ROM_LOAD( "gmmu28.bin",  0x200000, 0x200000, 0xcf6b23dc )
  1623.     ROM_LOAD( "gmmu29.bin",  0x400000, 0x200000, 0x8f27f5d3 )
  1624.     ROM_LOAD( "gmmu30.bin",  0x600000, 0x080000, 0xe9747c8c )
  1625.     /* codes 6800-7fff are explicitly skipped */
  1626. //    ROM_LOAD_GFX_EVEN( "gmmu64.bin",  0x700000, 0x100000, 0x57d77b33 )    // HALVES IDENTICAL
  1627. //    ROM_LOAD_GFX_ODD(  "gmmu65.bin",  0x700000, 0x100000, 0x05b8bdca )    // HALVES IDENTICAL
  1628.     /* wrong tiles:     gtmr    77e0 ; gtmralt    81c4 81e0 81c4 */
  1629.     ROM_LOAD( "sprites",     0x700000, 0x100000, 0x00000000 )
  1630.  
  1631.     ROM_REGION( 0x100000, REGION_SOUND1 )    /* Samples */
  1632.     ROM_LOAD( "gmmu23.bin",  0x000000, 0x100000, 0xb9cbfbee )    // 16 x $10000
  1633.  
  1634.     ROM_REGION( 0x100000, REGION_SOUND2 )    /* Samples */
  1635.     ROM_LOAD( "gmmu24.bin",  0x000000, 0x100000, 0x380cdc7c )    //  2 x $40000 - HALVES IDENTICAL
  1636.  
  1637. ROM_END
  1638.  
  1639.  
  1640. /*    This version displays:
  1641.  
  1642.     tb05mm-eu "1000 miglia"
  1643.     master up= 94/09/06 14:49:19            */
  1644.  
  1645. ROM_START( gtmre )
  1646.  
  1647.      ROM_REGION( 0x100000, REGION_CPU1 )            /* 68000 Code */
  1648.     ROM_LOAD_EVEN( "gmmu2.bin", 0x000000, 0x080000, 0x36dc4aa9 )
  1649.     ROM_LOAD_ODD(  "gmmu1.bin", 0x000000, 0x080000, 0x8653c144 )
  1650.  
  1651.      ROM_REGION( 0x010000, REGION_CPU2 )            /* MCU Code */
  1652.     ROM_LOAD( "mcu_code",  0x000000, 0x010000, 0x00000000 )
  1653.  
  1654.     ROM_REGION( 0x200000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (scrambled) */
  1655.     ROM_LOAD( "gmmu52.bin",  0x000000, 0x200000, 0xb15f6b7f )
  1656.  
  1657.     ROM_REGION( 0x900000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1658.     ROM_LOAD( "gmmu27.bin",  0x000000, 0x200000, 0xc0ab3efc )
  1659.     ROM_LOAD( "gmmu28.bin",  0x200000, 0x200000, 0xcf6b23dc )
  1660.     ROM_LOAD( "gmmu29.bin",  0x400000, 0x200000, 0x8f27f5d3 )
  1661.     ROM_LOAD( "gmmu30.bin",  0x600000, 0x080000, 0xe9747c8c )
  1662.     /* codes 6800-6fff are explicitly skipped */
  1663.     ROM_LOAD_GFX_EVEN( "gmmu64.bin",  0x700000, 0x100000, 0x57d77b33 )    // HALVES IDENTICAL
  1664.     ROM_LOAD_GFX_ODD(  "gmmu65.bin",  0x700000, 0x100000, 0x05b8bdca )    // HALVES IDENTICAL
  1665.  
  1666.     ROM_REGION( 0x100000, REGION_SOUND1 )    /* Samples */
  1667.     ROM_LOAD( "gmmu23.bin",  0x000000, 0x100000, 0xb9cbfbee )    // 16 x $10000
  1668.  
  1669.     ROM_REGION( 0x100000, REGION_SOUND2 )    /* Samples */
  1670.     ROM_LOAD( "gmmu24.bin",  0x000000, 0x100000, 0x380cdc7c )    //  2 x $40000 - HALVES IDENTICAL
  1671.  
  1672. ROM_END
  1673.  
  1674.  
  1675. /***************************************************************************
  1676.  
  1677.                         [ Great 1000 Miles Rally 2 ]
  1678.  
  1679. GMR2U48    1M        OKI6295: 00000-3ffff + chunks of 0x10000 with headers
  1680.  
  1681. GMR2U49    2M        sprites
  1682. GMR2U50    2M        sprites
  1683. GMR2U51    2M        sprites - FIRST AND SECOND HALF IDENTICAL
  1684.  
  1685. GMR2U89    2M        tiles
  1686. GMR1U90    2M        tiles
  1687. GMR2U90    IDENTICAL TO GMR1U90
  1688.  
  1689.  
  1690. ***************************************************************************/
  1691.  
  1692. ROM_START( gtmr2 )
  1693.  
  1694.      ROM_REGION( 0x100000, REGION_CPU1 )            /* 68000 Code */
  1695.     ROM_LOAD_EVEN( "maincode.1", 0x000000, 0x080000, 0x00000000 )
  1696.     ROM_LOAD_ODD(  "maincode.2", 0x000000, 0x080000, 0x00000000 )
  1697.  
  1698.     ROM_REGION( 0x400000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (scrambled) */
  1699.     ROM_LOAD( "gmr1u90.bin", 0x000000, 0x200000, 0xf4e894f2 )    // These are IDENTICAL
  1700.     ROM_LOAD( "gmr2u90.bin", 0x000000, 0x200000, 0xf4e894f2 )
  1701.  
  1702.     ROM_REGION( 0x800000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1703.     ROM_LOAD( "gmr2u49.bin",  0x000000, 0x200000, 0xd50f9d80 )
  1704.     ROM_LOAD( "gmr2u50.bin",  0x200000, 0x200000, 0x39b60a83 )
  1705.     ROM_LOAD( "gmr2u51.bin",  0x400000, 0x200000, 0xfd06b339 )
  1706.     ROM_LOAD( "gmr2u89.bin",  0x600000, 0x200000, 0x4dc42fbb )
  1707.  
  1708.     ROM_REGION( 0x100000, REGION_SOUND1 )    /* Samples */
  1709.     ROM_LOAD( "gmr2u48.bin", 0x000000, 0x100000, 0x1 )
  1710.  
  1711.     ROM_REGION( 0x100000, REGION_SOUND2 )    /* Samples */
  1712.     ROM_LOAD( "samples",  0x000000, 0x100000, 0x00000000 )
  1713.  
  1714. ROM_END
  1715.  
  1716.  
  1717.  
  1718.  
  1719. /***************************************************************************
  1720.  
  1721.                             [ Shogun Warriors ]
  1722.  
  1723. Shogun Warriors, Kaneko 1992
  1724.  
  1725.    fb010.u65           fb040.u33
  1726.    fb011.u66
  1727.    rb012.u67
  1728.    rb013.u68
  1729.  
  1730.                          fb001.u43
  1731.      68000-12            fb000.u42  m6295
  1732.     51257     fb030.u61  fb002.u44  m6295
  1733.     51257     fb031.u62  fb003.u45
  1734.  
  1735.  
  1736.                 fb021a.u3
  1737.                 fb021b.u4
  1738.                 fb022a.u5
  1739.    fb023.u7     fb022b.u6
  1740.    fb020a.u1    fb020b.u2
  1741.  
  1742.  
  1743. fb022b.u6               FIXED BITS (11111111)
  1744.  
  1745.  
  1746. ---------------------------------------------------------------------------
  1747.                                 Game code
  1748. ---------------------------------------------------------------------------
  1749.  
  1750. 102e04-7    <- !b80004-7
  1751. 102e18.w    -> $800000
  1752. 102e1c.w    -> $800002 , $800006
  1753. 102e1a.w    -> $800004
  1754. 102e20.w    -> $800008
  1755.  
  1756. ROUTINES:
  1757.  
  1758. 6622    print ($600000)
  1759.  
  1760. ***************************************************************************/
  1761.  
  1762. ROM_START( shogwarr )
  1763.  
  1764.      ROM_REGION( 0x040000, REGION_CPU1 )            /* 68000 Code */
  1765.     ROM_LOAD_EVEN( "fb030a.u61", 0x000000, 0x020000, 0xa04106c6 )
  1766.     ROM_LOAD_ODD(  "fb031a.u62", 0x000000, 0x020000, 0xd1def5e2 )
  1767.  
  1768.      ROM_REGION( 0x020000, REGION_CPU2 )            /* MCU Code */
  1769.     ROM_LOAD( "fb040a.u33",  0x000000, 0x020000, 0x4b62c4d9 )
  1770.  
  1771.     ROM_REGION( 0x400000, REGION_GFX1 | REGIONFLAG_DISPOSE )    /* Tiles (scrambled) */
  1772.     ROM_LOAD( "fb010.u65",  0x000000, 0x100000, 0x296ffd92 )
  1773.     ROM_LOAD( "fb011.u66",  0x100000, 0x080000, 0x500a0367 )    // ?!
  1774.     ROM_LOAD( "rb012.u67",  0x200000, 0x100000, 0xbfdbe0d1 )
  1775.     ROM_LOAD( "rb013.u68",  0x300000, 0x100000, 0x28c37fe8 )
  1776.  
  1777.     ROM_REGION( 0x600000, REGION_GFX2 | REGIONFLAG_DISPOSE )    /* Sprites */
  1778.     ROM_LOAD( "fb020a.u1",  0x000000, 0x080000, 0xda1b7373 )
  1779.     ROM_LOAD( "fb022a.u5",  0x080000, 0x080000, 0x60aa1282 )
  1780.     ROM_LOAD( "fb020b.u2",  0x100000, 0x100000, 0x1 )
  1781.     ROM_LOAD( "fb021a.u3",  0x200000, 0x100000, 0x1 )
  1782.     ROM_LOAD( "fb021b.u4",  0x300000, 0x100000, 0x1 )
  1783.     ROM_LOAD( "fb023.u7",   0x400000, 0x100000, 0x132794bd )
  1784.     ROM_LOAD( "fb022b.u6",  0x500000, 0x100000, 0x00000000 )
  1785.  
  1786.     ROM_REGION( 0x100000, REGION_SOUND1 )    /* Samples */
  1787.     ROM_LOAD( "fb000e.u42",  0x000000, 0x080000, 0x969f1465 )    // 2 x $40000
  1788.     ROM_LOAD( "fb001e.u43",  0x080000, 0x080000, 0xf524aaa1 )    // 2 x $40000
  1789.  
  1790.     ROM_REGION( 0x100000, REGION_SOUND2 )    /* Samples */
  1791.     ROM_LOAD( "fb002.u44",   0x000000, 0x080000, 0x05d7c2a9 )    // 2 x $40000
  1792.     ROM_LOAD( "fb003.u45",   0x080000, 0x080000, 0x405722e9 )    // 2 x $40000
  1793.  
  1794. ROM_END
  1795.  
  1796.  
  1797. void init_shogwarr(void)
  1798. {
  1799.     /* Code patches */
  1800. #if 0
  1801.     unsigned char *RAM = memory_region(REGION_CPU1);
  1802.     WRITE_WORD(&RAM[0x0039a], 0x4e71);    // 200000 test
  1803.     WRITE_WORD(&RAM[0x003e6], 0x4e71);    // 20030a test
  1804.     WRITE_WORD(&RAM[0x223a8], 0x6000);    // rom test
  1805. #endif
  1806.  
  1807.     init_kaneko16();
  1808.  
  1809. /*
  1810.     ROM test at 2237e:
  1811.  
  1812.     the chksum of 00000-03fffd = $657f is added to ($200042).w
  1813.     [from shared ram]. The result must be $f463 [=($3fffe).w]
  1814.  
  1815.     Now, $f463-$657f = $8ee4 = byte sum of FB040A.U33 !!
  1816.  
  1817.     So, there's probably the MCU's code in there, though
  1818.     I can't id what kind of CPU should run it :-(
  1819. */
  1820. }
  1821.  
  1822.  
  1823.  
  1824. /***************************************************************************
  1825.  
  1826.                                 Game drivers
  1827.  
  1828. ***************************************************************************/
  1829.  
  1830. GAMEX( 1991, berlwall, 0,        berlwall, berlwall, kaneko16, ROT0_16BIT, "Kaneko", "The Berlin Wall (set 1)", GAME_WRONG_COLORS )
  1831. GAMEX( 1991, berlwalt, berlwall, berlwall, berlwalt, kaneko16, ROT0_16BIT, "Kaneko", "The Berlin Wall (set 2)", GAME_WRONG_COLORS )
  1832. GAMEX( 1992, shogwarr, 0,        shogwarr, shogwarr, shogwarr, ROT0,       "Kaneko", "Shogun Warriors", GAME_NOT_WORKING )
  1833. GAME ( 1994, gtmr,     0,        gtmr,     gtmr,     kaneko16, ROT0_16BIT, "Kaneko", "Great 1000 Miles Rally" )
  1834. GAME ( 1994, gtmre,    gtmr,     gtmr,     gtmr,     kaneko16, ROT0_16BIT, "Kaneko", "Great 1000 Miles Rally (Evolution Model)" )
  1835. GAMEX( 1995, gtmr2,    0,        gtmr,     gtmr,     kaneko16, ROT0,       "Kaneko", "Great 1000 Miles Rally 2", GAME_NOT_WORKING )
  1836.